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Reducing Qrr in high-voltage SuperJunction MOSFETs by using the cascode configuration

dc.contributor.authorCampo Rodríguez, Juan Carlos 
dc.contributor.authorRodríguez Alonso, Alberto 
dc.contributor.authorGonzález Lamar, Diego 
dc.contributor.authorRoig, J.
dc.contributor.authorBauwens, Filip
dc.date.accessioned2017-10-31T10:48:27Z
dc.date.available2017-10-31T10:48:27Z
dc.date.issued2017
dc.identifier.isbn978-1-5090-5366-7
dc.identifier.urihttp://hdl.handle.net/10651/44189
dc.descriptionIEEE Annual Applied Power Electronics Conference and Exposition (APEC) (32nd. 2017. Tampa)
dc.description.sponsorshipThis work has been supported by the Spanish Government under Project MINECO-13-DPI2013-47176-C2-2-R, MINECO-15-DPI2014-56358-JIN, the scholarship FPU14/03268 and the Principality of Asturias under the Project FC-15- GRUPIN14-143 and by European Regional Development Fund (ERDF) grants.
dc.format.extentp. 1970-1977
dc.language.isoeng
dc.relation.ispartofConference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
dc.rights©,
dc.rightsCC Reconocimiento – No Comercial – Sin Obra Derivada 4.0 Internacional
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/
dc.sourceScopus
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85020125660&doi=10.1109%2fAPEC.2017.7930968&partnerID=40&md5=de672ae6a35c0018d82cab60ea78031b
dc.titleReducing Qrr in high-voltage SuperJunction MOSFETs by using the cascode configuration
dc.typeconference outputspa
dc.identifier.doi10.1109/APEC.2017.7930968
dc.relation.projectIDMINECO-13-DPI2013-47176-C2-2-R
dc.relation.projectIDMINECO-15-DPI2014-56358-JIN
dc.relation.projectIDFPU14/03268
dc.relation.projectIDFC-15- GRUPIN14-143
dc.relation.publisherversionhttp://dx.doi.org/10.1109/APEC.2017.7930968
dc.rights.accessRightsopen access
dc.type.hasVersionAM


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