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Steady-state analysis and modelling of power factor correctors with appreciable voltage ripple in the output-voltage feedback loop to achieve fast transient response

dc.contributor.authorSebastián Zúñiga, Francisco Javier 
dc.contributor.authorGonzález Lamar, Diego 
dc.contributor.authorHernando Álvarez, Marta María 
dc.contributor.authorRodríguez Alonso, Alberto 
dc.contributor.authorFernández González, Arturo José 
dc.date.accessioned2013-11-14T09:43:02Z
dc.date.available2013-11-14T09:43:02Z
dc.date.issued2009
dc.identifier.citationIEEE Transactions on Power Electronics, 24(11), p. 2555-2566 (2009); doi:10.1109/TPEL.2009.2027707
dc.identifier.issn0885-8993
dc.identifier.urihttp://hdl.handle.net/10651/19536
dc.description.abstractThe classical design of an active power factor corrector (PFC) leads to slow transient response in this type of converter. This is due to the fact that the compensator placed in the output-voltage feedback loop is usually designed to have narrow bandwidth to filter the voltage ripple of twice the line frequency coming from the PFC output. This feedback loop is designed with this filtering effect because a relatively high ripple would cause considerable distortion in the reference of the line current feedback loop, and hence in the line current. However, the transient response of the PFC can be substantially improved if the bandwidth of this compensator is relatively wide, thus permitting certain distortion in the line current that leads to a tradeoff between transient response (and hence voltage ripple at the output of the compensator) and harmonic content in the line current. As a consequence of the voltage ripple at the output of the compensator (which is considered the control signal), both the static and the dynamic behaviors of the PFC change in comparison with the standard case, i.e., with no voltage ripple on the control signal. The static behavior of a PFC with appreciable voltage ripple in the output-voltage feedback loop is studied in this paper using two parameters: the amplitude of the relative voltage ripple on the control signal and its phase lag angle. The total power processed by the PFC depends on these parameters, which do not vary with the load and which determine the total harmonic distortion and the power factor at the input of the PFC. Furthermore, these parameters also determine the maximum power that can be processed by the converter while still complying with EN 61000-3-2 regulations for Class A and Class B equipment. When the converter comply with the aforementioned regulations for Class C or Class D equipment, however, the compliance does not depend on the power processed by the PFC. In the case of Class C equipment, not all the possible c- - ombinations of the relative ripple of the control signal and its phase lag angle manage to comply with these regulations. Finally, the study was verified by simulation and in a real prototypeeng
dc.description.sponsorshipThis work has been supported by the Spanish Ministry of Education and Science under Project TEC2007-66917/MIC and Grant AP2006-04777
dc.format.extentp. 2555-2566spa
dc.language.isoeng
dc.relation.ispartofIEEE Transactions on Power Electronics, 24(11)spa
dc.rights© 2009 IEEE
dc.titleSteady-state analysis and modelling of power factor correctors with appreciable voltage ripple in the output-voltage feedback loop to achieve fast transient responseeng
dc.typejournal article
dc.identifier.doi10.1109/TPEL.2009.2027707
dc.relation.publisherversionhttp://dx.doi.org/10.1109/TPEL.2009.2027707spa
dc.rights.accessRightsopen access
dc.type.hasVersionAM


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