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Optimized synchronous rectification stage for low output voltage (3.3 V) DC/DC conversion
dc.contributor.author | Cobos, J. A. | |
dc.contributor.author | García, O. | |
dc.contributor.author | Sebastián Zúñiga, Francisco Javier | |
dc.contributor.author | Uceda, Javier | |
dc.contributor.author | Aldana, F. | |
dc.date.accessioned | 2015-07-31T08:32:26Z | |
dc.date.available | 2015-07-31T08:32:26Z | |
dc.date.issued | 1994-06 | |
dc.identifier.isbn | 0-7803-1859-5 | |
dc.identifier.uri | http://hdl.handle.net/10651/32463 | |
dc.format.extent | p. 902-908 | spa |
dc.language.iso | eng | spa |
dc.publisher | IEEE | spa |
dc.relation.ispartof | 25th Annual IEEE Power Electronics Specialists Conference, PESC '94 Record, 2 | spa |
dc.title | Optimized synchronous rectification stage for low output voltage (3.3 V) DC/DC conversion | spa |
dc.type | conference output | spa |
dc.identifier.doi | 10.1109/PESC.1994.373786 | |
dc.relation.publisherversion | http://dx.doi.org/10.1109/PESC.1994.373786 | spa |
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